Avaya Definity TN765 Processor Interface.
More Information
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Integrates the tone generator, tone detection, system clock, and synchronization functions onto one circuit pack for use in standard, high, and critical reliability systems
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Provides 4 data links to the Time Division Multiplexing (TDM) bus and a link through the memory bus to the processor
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Interfaces the 3B2 MSA, DCS, ISDN, and Audix Interface service
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Allows direct access to one data link from an EIA port on the circuit pack
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Other data links connect to a digital line circuit and a PDM or TDM to access an MSA, DCS, CMS, ISDN, or Audix
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Data links can connect to DS1 tie trunks to access DCS or ISDN applications
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